This invention relates to a clock regenerator for regenerating a clock signal from a received data signal.
As will later be described in more detail with reference to a few figures of the accompanying drawing, a conventional clock regenerator for an input data signal comprises a controllable frequency divider for producing a regenerated clock signal in response to a local signal of a stable frequency. According as the regenerated clock signal leads or lags behind the input data signal, the frequency divider is controlled to divide the stable frequency at a smaller or a greater frequency division ratio than a normal one, respectively, to phase-synchronize the regenerated clock signal with the input data signal. When a difference between the smaller or greater frequency division ratio and the normal one is smaller, a longer time is necessary to achieve the phase synchronizm. When the difference is greater, a shorter time is sufficient. It is, however, inevitable in the latter event that jitter occurs in the phase of the regenerated clock signal and hardly disappears even when there is no jitter in the phase of the input data signal.